The present invention is related to systems and methods for synchronizing a semiconductor device, and more particularly to systems and methods for generating a clock signal.
Semiconductor devices often rely on a clock signal to synchronize operation of circuitry implemented within the device. In some cases, such clock signals are provided external to the device, while in other cases they are generated as part of the circuitry of the semiconductor device. Various approaches have been utilized for such internal clock generation including phase lock loops using a reference signal and driving a voltage controlled oscillator. In general, such clock generation circuitry function over limited ranges. Such a limited range of operation is often acceptable for a particular design, but in some cases a greater range of operation is desired.
As an example, one existing voltage controlled oscillator 100 utilizing a preset current and discrete capacitor to set the oscillation frequency is depicted in FIG. 1. Voltage controlled oscillator 100 includes a series of two PFET transistors 102, 104 and NFET transistors 106, 108 that operate as a current mirror either sinking or sourcing current to/from a discrete capacitor 110. In operation, a preset current 112 flows either into or out of discrete capacitor 110. In particular, when the gates of transistors 104, 106 are asserted low, preset current 112 is sourced to discrete capacitor 110 via transistors 102, 104. Once discrete capacitor 110 is sufficiently charged to trigger a defined level of a Schmidt trigger 120, an output of Schmidt trigger 120 asserts low and in turn an output of a succeeding inverter 130 asserts high. The output of inverter 130 is provide to the gates of transistors 104, 106 such that preset current 112 is discharged from discrete capacitor 110 via transistors 106, 108. Once sufficient charge is removed from discrete capacitor 110 a lower voltage threshold of Schmidt trigger 120 is achieved causing the output of Schmidt trigger 120 to assert high. In turn, the output of inverter 130 is asserted low causing preset current 112 to flow into discrete capacitor 110 via transistors 102, 104. Thus, an oscillation within a particular range defined by preset current 112 and discrete capacitor 110 is achieved.
The actual oscillation frequency is somewhat controlled by an input 160 that is capable of rendering small adjustments in preset current 112 via a current mirror and enable circuit consisting of transistors 173-179 and an inverter 150. Further, a clock output 180 may be provided via an inverting buffer 140. The range over which the oscillation frequency may be adjusted using input 160 is typically limited due to various sources of distortion and the value of discrete capacitor 110. This limits the operational utility of voltage controlled oscillator 100.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for clock generation.